This invention relates in general to computer memory testing, and more particularly, a memory tester for testing memory in a motherboard-compatible environment.
Computer memory testing is becoming more demanding given the higher operational speeds of processors, and associated memory. Therefore more effective and efficient means are needed to perform testing while minimizing downtime during a production environment. Conventional memory testing techniques in a personal computer (PC) involve cycling system power which is cumbersome and time consuming.
All computer hardware has to work with software through an interface. A computer system""s basic input/output system (BIOS) is responsible for booting the computer by providing a basic set of instructions. The code stored in a BIOS chip performs the power-on self-test (POST) routine at startup, then establishes communication with floppy disks, hard disks, keyboards, ports, and expansion slots before finally handing over control to the operating system. The BIOS gives the PC a basic software starter-kit from which the central processing unit (CPU) becomes xe2x80x9cawarexe2x80x9d of all peripheral devices which are a part of the system. When the BIOS boots to establish basic system awareness, it provides an interface to the underlying hardware for the operating system in the form of a library of interrupt handlers. Any device requesting attention by the CPU sends a signal out on an interrupt line to an interrupt controller, which then signals the CPU that the device needs attention. The POST process also performs a basic test of the physical memory (e.g., DRAM). This is typically evidenced on a computer display during boot-up by a rapidly incrementing number indicating that each memory location of the physical memory is being checked. Upon completion of a successful check, the BIOS continues the boot-up procedure by establishing all necessary handshaking with peripheral devices.
In addition to physical memory, typically in the form of DRAM, the PC has faster memory called cache memory. Cache memory is a special high-speed memory used to accelerate processing of the most recently used memory instructions by the CPU. The CPU can access instructions and data located in cache memory much faster than instructions and data in the main DRAM memory. For example, on a typical 100-MHz system board, it takes the CPU as much as one-hundred-and-eighty nanoseconds to obtain information from physical memory, compared to just forty-five nanoseconds from the cache memory. Therefore, the more instructions and data the CPU can access directly from cache memory, the faster the computer can run. Cache memory is categorized into external secondary (L2 cache) and internal primary (L1 cache). The xe2x80x9cbrainxe2x80x9d of a cache memory system is called the cache memory controller. When a cache memory controller retrieves an instruction from physical memory, it also takes back the next several instructions to cache memory.
This occurs because there is a high likelihood that the adjacent instructions will also be needed. This increases the chance that the CPU will find the instruction it needs in cache memory, thereby enabling the computer to run faster.
A PC consists of different functional parts installed on its motherboard: ISA (Industry Standard Architecture) and PCI (Peripheral Component Interface) slots, memory, cache memory, keyboard plug, etc. Not all of these are present on every motherboard. One or more interface circuits enable a set of instructions so the CPU can communicate with other parts of the motherboard. Most of the discrete chips: PIC (Programmable Interrupt Controller), DMA (Direct Memory Access), MMU (Memory Management Unit), cache, and so on, are packed together on one, two, or three chips which are cooperatively known as the xe2x80x9cchipset.xe2x80x9d In some well-integrated motherboards, the only components present are the CPU, the two BIOS chips (system BIOS and keyboard BIOS), one chipset IC, cache memory, physical memory (e.g., DRAM), and a clock chip.
A method of testing memory of a system is disclosed which operates the system from a second area of system address space which is outside of a first area of system address space, the system having one or more physical memory devices associated with the first area of system address space. The memory locations associated with the first area of the system address space are tested for predetermined characteristics after which the one or more tested physical memory devices are replaced with respective untested physical memory devices without dropping power to the system, and tested by repeating the test cycle. The system is prevented from operating in the first area of system address space and forced""to operate from the second area, thereby preventing system interruptions when replacing the physical memory devices for testing.